CN
P270 Series

P270 is an 8-stage, dual-issue, highly efficient in-order pipeline compatible with the RISC-V RV64GBCV ISA.

P270 Key Features

256-bit vector length processor

  • Variable length operations, up to 256-bits of data per cycle, with dynamic vector length configuration
  • Ideal balance of control and data parallel compute

Performance

  • 5.75 CoreMarks/MHz
  • 3.25 DMIPS/MHz
  • SpecINT 2K6 = 4.6

Scalar processing built from U7 series core

  • Multi-layer Caching support for optimum data movement
  • Stride Prefetcher
  • Virtual memory support, up to 48-bit addressing

High performance, flexible connectivity to SoC peripherals

Multi-core processor configuration with up to 4-cores

Implements RISC-V Vectors v1.0-rc version

Dual issue scalar unit runs concurrently with vector unit

Key vector unit attributes

  • VLEN = 256. DLEN = 128 (datapath width). ELEN = 64 (datatypes)
  • Separate memory and ALU pipelines for concurrent operation
  • Vector operations, decoded and Queued in Vector Unit for parallel operation of Scalar and Vector units

Vector ALU

  • 128b ALU can perform 2x64b, 4x32b, 8x16b, 16x8b ops/cycle
  • Integer and Floating point data types supported

Vector Loads/Stores are 128b/cycle

  • L2 cache treated as primary memory
  • Load from L1 cache, initiates L2 cache load in parallel, minimizing L1 cache miss impact
Target Markets

Enterprise Switching/Routing/Storage, Smart NICs

Edge Analytics, Big-Data Analytics

Autonomous Machines

Edge Compute

5G Infrastructure/Base Stations

AR/VR/MR/XR

P550

P550 features a thirteen-stage, triple-issue, out-of-order pipeline compatible with the RISC-V RV64GBC ISA.

P550 Key Features

Breakthrough RISC-V performance

  • 3x Performance per mm2 compared to Cortex-A75
  • Performance >8.6 SpecINT2k6/GHz, Higher single threaded performance than Cortex-A75

P550 Core Architectural Features

  • RV64GBC capable core with Sv39/Sv48 Virtual Memory Support
  • Three Issue, out-of-order Pipeline tuned for scalable performance
  • Private L2 Caches and Streaming Prefetcher for improved memory performance
  • SECDED ECC with Error Reporting

Enabling next generation applications

  • Cache stashing to L3 for tightly coupled accelerators
  • Mix+Match capable for real-time deterministic workloads
Target Markets

Enterprise Switching/Routing/Storage, Smart NICs

Edge Analytics, Big-Data Analytics

Autonomous Machines

Edge Compute

5G Infrastructure/Base Stations

AR/VR/MR/XR